1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device which can improve the anti-diffusion properties of a barrier metal layer formed between a metal wire and an insulating film and prevent an increase in resistance by the barrier metal layer.
2. Discussion of Related Art
Generally, a metal wire is formed in such a way that a dual damascene patterns having a trench and a contact hole (or a via hole) is formed in an interlayer insulating film through a dual damascene process and is then filled with a metal material. At this time, a barrier metal layer for preventing a metal component of the metal wire from diffusing into the interlayer insulating film is formed between the metal wire and the interlayer insulating film.
The degree that the metal component is diffused into the interlayer insulating film varies depending on the material of the metal wire. In case of aluminum (Al), it has been known that diffusion of Al into SiO2 used as an insulating film never occurs. Therefore, in case of an Al metal wire, it is possible to form a barrier metal layer thinly. As such, the barrier metal layer does not greatly influence the electrical properties.
On the contrary, copper (Cu) is easily diffused into SiO2 used as the insulating film. Cu diffused into a device through the insulating film exists within Si as a deep level. That is, Cu acts as a deep level dopant within Si, thus forming several acceptor and donor levels within the forbidden band of Si. These deep levels function as a source of generation-recombination to cause the leakage current. In worse case, it causes the device to be defective.
Accordingly, if a metal wire is formed using a metal material such as Cu that is easily diffused, there is a need for a barrier metal for an insulating material at the sidewalls as well as the bottom brought into contact with a heterogeneous metal.
A metal wire process using Cu is a prerequisite process as the integration level of a device is increased by the electrical properties. In this case, as the aspect ratio of the trench or the contact hole is increased due to the increased level of integration, the deposition characteristic of the barrier metal layer is degraded. Therefore, there is a problem that a step coverage characteristic is poor.
Recently, HCM TaNx, SIP TaNx and so on and an advanced PVD have been employed. It is thus considered that there is no significant problem in forming the barrier metal layer up to a 90 nm process. In the future, however, in a 90 nm or less process, it would be impossible to apply the barrier metal layer of the PVD method due to fine pores contained in low-dielectric insulating materials as well as reduction in the pattern size.
A sole solution for overcoming this problem is to form the barrier metal layer through an atomic layer deposition (hereinafter, referred to as “ALD”) method. The ALD method is one in which gases to be reacted are introduced into a chamber in turn one by one to deposit atomic layers one by one, unlike the CVD method. The ALD method is superior in the step coverage characteristic. If the design rule is 90 nm or less, however, the barrier metal layer formed by the ALD method has a very thin thickness of several tens Å or less. It is thus difficult to expect good metal (particularly, Cu) anti-diffusion properties.